1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device with high integration and high-speed memory access.
2. Description of the Related Art
Lately, non-volatile memory devices capable of electrically erasing and overwriting data have become larger and highly integrated. Generally, a cell transistor used in a non-volatile memory device has a floating gate and a control gate. These memory devices are largely divided into two types of devices according to the connection pattern employed therein, namely a NOR type and a NAND type device.
Specifically, the NOR type non-volatile memory device is constructed such that two memory cells, facing each other, share a bit line contact as well as a source line. Thus, a plurality of memory cells are connected to one bit line in parallel. Furthermore, a channel hot electron method is employed when storing data and a Fowler-Nordheim (F-N) tunneling method is employed when data is erased. To achieve such operations, the NOR type non-volatile memory device requires a large amount of cell current, which is, unfortunately, disadvantageous for high integration. However, this type of non-volatile memory device has the advantage of easily providing for high-speed memory access.
The NAND-type non-volatile memory device is also constructed such that two cell strings share a bit line contact and one source line. However, in this type of memory device, a cell string is arranged such that a plurality of cell transistors are serially connected to a bit line. In the NAND type non-volatile memory device, F-N tunneling is generated between a substrate and a floating gate of the memory cell transistor according to a voltage applied to a control gate of the memory cell and to the substrate. Thereby, either a storage or an erase operation can be performed depending on the voltage applied. Because only a small amount of cell current is required for this type of memory device, high-speed operation is more difficult to achieve but high integration within the memory device is facilitated. Consequently, since a NAND-type non-volatile memory cell array is more highly integrated than a NOR-type non-volatile memory cell array, it is preferred for attaining a high storage capacity memory device.
FIG. 1 shows the vertical structure of a unit string of a conventional single bit line NAND-type flash memory device. Referring to FIG. 1, the conventional single bit line NAND-type flash memory device is constructed with an n-well 3 formed on a p-type substrate 1 (otherwise, a p-well may be formed on the n-type substrate), and a p-well 5 formed in the n-well 3 (hereinafter, to be referred to as a "pocket p-well"). Next, an active region and a field isolating region (not shown) are formed on a bulk where the pocket p-well 5 is formed using conventional LOCOS technology. A tunnel oxide (not shown) for inputting and outputting electrons for the purpose of storing or erasing data of a cell is formed on the active region with a thickness of 80 .ANG. to 100 .ANG.. Thereafter, polysilicon 7, to be used as a floating gate, is separately formed in every cell and an ONO (Oxide-Nitride-Oxide) film 9, functioning as an interpoly isolating film, is formed with a thickness of 150 .ANG. to 200 .ANG.. Polycide 11 is then deposited for a selection line and a plurality of word lines, each word line used as a control gate of one of the memory cells in a string. Ions are implanted to form a source or drain 13 for each of a plurality of transistors and for each of the memory cells. Finally, a metal wiring 15 is formed to be used as a bit line.
In the NAND-type flash memory device, a unit memory cell operates using electron migration by F-N tunneling through the tunnel oxide. When an operating voltage is applied between the control gate and the bulk silicon (the pocket p-well), a predetermined voltage is induced into the floating gate by a coupling ratio of a capacitor Ci, comprised of an interpoly isolating film between the control gate and the floating gate, to a tunnel oxide capacitor Ct, formed between the bulk silicon and the floating gate. Specifically, during a programming operation, Vf=(Ci.times.Vpgm)/(Ct+Ci), and during an erasing operation, Vf=(Ct.times.Vers)/(Ct+Ci); where Vf is a voltage induced to the floating gate, Vpgm is a program voltage applied to the control gate, and Vers is an erase voltage applied to the bulk silicon. Accordingly, electron migration occurs by F-N tunneling through the tunnel oxide according to a voltage difference between the floating gate and the bulk silicon. A cell array is formed in the pocket p-well 5 for the purpose of separating an erasing voltage Vers of about 20V, which is applied to the bulk silicon during the erasing operation of a cell, from the bulk operating area of peripheral circuits.
FIG. 2 is a schematic circuit diagram of the conventional single bit line NAND-type flash memory device shown in FIG. 1 showing only two strings 20, representative of all the strings, each string connected to a bit line B/L1 and B/L2. Referring to FIG. 2, each of a plurality of unit strings 20 is constructed such that a plurality of unit memory cells MC1 through MC16 are serially connected between a drain of a bit line select transistor M1 and a source of a source line select transistor M2. The bit line select transistor M1 has a gate connected to a bit line select line SSL and a source connected to a respective one of the bit lines B/L1 or B/L2. The source line select transistor has a gate connected to a source line select line GSL and a drain connected to a common source line CSL. This arrangement thereby connects each of the bit lines B/L1 and B/L2 to the unit memory cells MC1 through MC16 of one of the unit strings.
FIG. 3 is a timing diagram illustrating a method of driving the conventional single bit line NAND-type flash memory device. The operation of the conventional single bit line NAND-type flash memory device shown in FIGS. 1 and 2 will now be described more completely with reference to FIG. 3. Specifically, a program operation for storing electrons in the floating gate of a cell is performed by applying a voltage to a selected cell. For example, a program voltage Vpgm is applied to a selected word line W/L3 of a selected unit memory cell A. A pass voltage Vpass is applied to the non-selected word lines W/Ln (1.ltoreq.n.ltoreq.16, n.noteq.3) and to the bit line select line SSL. Finally, a ground voltage of 0V is applied to a selected bit line B/L1 and to the source line select line GSL while a precharge voltage Vpi is applied to a non-selected bit line B/L2. Accordingly, electrons are injected from the bulk silicon to the floating gate of the selected unit memory cell A by F-N tunnelling through the tunnel oxide according to an electrical field created by the difference between the program voltage Vpgm on the selected word line W/L3 and the ground voltage on the selected bit line B/L1.
At this time, although other cells are connected to the selected word line W/L3 (i.e., cell B), the cells connected to non-selected bit lines (i.e., B/L2), are not programmed. Specifically, since the pass voltage Vpass is applied to the bit line select line SSL and the non-selected word lines W/Ln (1.ltoreq.n.ltoreq.16, n.noteq.3), and further, since the precharge voltage Vpi, applied to the non-selected bit line B/L2, is induced to a channel of the non-selected cell B, the intensity of the electrical field created by the program voltage Vpgm of the selected word line W/L3 is reduced. The electron tunneling effect is thereby suppressed and programming of the non-selected cells connected to the selected word line W/L3 is prevented.
An erase operation, for removing electrons from the floating gate of one of the unit memory cells, is performed by applying a ground voltage of 0V to the selected word line W/L3 and an erase voltage Vers of about 20V to the bulk silicon. Accordingly, electrons of the floating gate are removed by the electrical field created by the erase voltage Vers and holes are thereby injected into the floating gate of the memory cell.
A read operation, for reading a cell data value from one of the unit memory cells, utilizes the fact that the threshold voltage Vth of a cell becomes about +1V when electrons are stored in the floating gate of the cell and becomes about -3V when holes are stored therein. Specifically, the read operation is performed by applying a ground voltage of 0V to a selected word line W/L3, thereby reading the cell data value of logic "0" or "1" according to presence or absence of a current path through a selected cell.
When the operation scheme of the conventional single bit line NAND-type flash memory device is used, the precharge voltage Vpi applied to the non-selected bit lines must be higher than a supply voltage Vcc in order to prevent program disturbances in a high-density flash memory device. Therefore, in order to generate a high enough precharge voltage Vpi, a technique for pumping charges to the supply voltage Vcc using a capacitor is generally employed. Since the capacity of the capacitor is determined by a bit line capacitance, the capacitor for pumping charges must be larger when the bit line capacitance is increased as a result of high integration. Consequently, when the bit line capacitance is increased, the chip area occupied by the charge pumping capacitor also increases, and the time required for charging the non-selected bit lines with the precharge voltage Vpi increases, thereby causing an increase in the programming time. To solve this problem, a self-boosting technique is frequently used.
FIGS. 4A and 4B are timing diagrams illustrating a method of driving the conventional single bit line NAND-type flash memory device of FIGS. 1 and 2 using the prior art self-boosting technique. Particularly, FIG. 4A illustrates conditions for a program operation and FIG. 4B illustrates conditions for a read operation.
Referring to FIGS. 2, 3 and 4A, the self-boosting technique during the program operation is performed by applying the supply voltage Vcc to the non-selected bit line B/L2 as well as to the bit line select line SSL. The program voltage Vpgm is applied to the selected word line W/L3, while the pass voltage Vpass is applied to the non-selected word lines W/Ln (1.ltoreq.n.ltoreq.16, n.noteq.3). Finally, the ground voltage of 0V is applied to the selected bit line B/L1, the bulk silicon, and the source line select line GSL. Accordingly, the precharge voltage Vpi is self-boosted to the channel of a non-selected string. When this self-boosting technique is employed, therefore, a higher voltage, exceeding the supply voltage, is only required to be applied to the word line. Consequently, a charge pumping capacitor is required only for generating the higher voltage to be applied to the word line; as compared with the conventional art which necessitated charge pumping capacitors for generating higher voltages for the bit line as well as the word line. The chip area occupied by the charge pumping capacitor, as well as the time for charging the bit line with the precharge voltage Vpi, thereby decreases.
FIG. 5 shows a layout of the conventional single bit line NAND-type flash memory device shown in FIGS. 1 and 2, in which like symbols are used to designate like or equivalent portions of the memory device. Referring to FIG. 5, it is difficult to form a bit line 15 by a general metal wiring process in the conventional single bit line NAND-type flash memory device which will satisfy the desire for high integration. Therefore, a modified process is used which employs a poly pad layer on a contact region 17. Unfortunately, this results in an increase in processing steps. To solve this problem, a shared bit line cell technique has been proposed in which two neighboring strings share a single bit line.
FIG. 6 is a circuit diagram of a conventional NAND-type flash memory device adopting the shared bit line technique and the self-boosting technique. Only two of a plurality of string blocks 30, representative of all the string blocks in the device, are shown. Referring to FIG. 6, a first and a second string 30a and 30b of each of the string blocks 30 share a single bit line B/L1 or B/L2, respectively. The first string 30a is constructed such that a first and a second bit line select transistor M1 and M2, respectively, a plurality of unit memory cells MC1 through MC16, and a first source line select transistor M5 are connected in series between one of the bit lines B/L1 or B/L2 and the common source line CSL. Also, the second string 30b is similarly constructed such that third and fourth bit line select transistors M3 and M4, respectively, a plurality of unit memory cells MC17 through MC32, and a second source line select transistor M6 are connected in series between another one of the bit lines B/L1 or B/L2 and the common source line CSL.
FIGS. 7A through 7C are timing diagrams illustrating a method of driving the conventional NAND-type flash memory device shown in FIG. 6. Particularly, FIG. 7A illustrates conditions for the erase operation, FIG. 7B illustrates conditions for the program operation, and FIG. 7C illustrates conditions for the read operation. The operation of the conventional NAND-type flash memory device shown in FIG. 6, adopting the shared bit line cell technique and the self-boosting technique, will now be described with reference to FIG. 6, and FIGS. 7A to 7C.
Referring to FIGS. 6 and 7A, during an erase operation, electrons on the floating gates of all the cells connected to all word lines in the selected strings 30a and 30b are erased. The erase operation is performed by applying an erase voltage Vers of about 20V to the bulk where the cell array is formed and a ground voltage of 0V to all word lines W/Ln (1.ltoreq.n.ltoreq.16) of the selected strings 30a and 30b. The erase voltage Vers is also applied to the bit line select lines SSL1 and SSL2 and to the source line select line GSL. At this time, all word lines of non-selected strings (not shown), the bit lines B/L1 and B/L2, and common source line CSL are floated. Accordingly, electrons on the floating gates are erased by F-N tunneling through the tunnel oxide because of a voltage difference between the erase voltage Vers applied to the bulk and the ground voltage applied to the word lines W/Ln (1.ltoreq.n.ltoreq.16) of the selected strings. The threshold voltage Vth of all the cells in the selected strings 30a and 30b is thereby lowered to about -3V.
Referring to FIGS. 6 and 7B, a program operation comprises a step of pre-charging a non-selected bit line B/L2 in order to prevent a programming disturbance of non-selected cells, a programming step, and a program verifying step consisting of reading each cell in order to verify whether or not the selected cell has been adequately programmed. During the program operation, the supply voltage Vcc is first applied to each of the bit lines B/L1 and B/L2, while the pass voltage Vpass, which is higher than or equal to the supply voltage Vcc and lower than the program voltage Vpgm, is applied to the word lines W/L1 to W/L16. Thereby, the voltage applied to the bit lines B/L1 and B/L2 is precharged onto the channels of the cells. The program voltage Vpgm and the ground voltage of 0V are then sequentially applied to the selected word line W/L2, the bit line select line SSL2, and selected bit line B/L1, resulting in the precharge voltage Vpi, which was induced into the channel of the selected cell C, being discharged to be kept at 0V. Finally, electrons are injected into the floating gate of the selected cell C from the bulk silicon via the tunnel oxide as the program voltage Vpgm is applied to the selected word line W/L2 (about 18V). The threshold voltage of the selected cell C is thereby changed to about +1V, such that the selected cell C is programmed.
When the program voltage Vpgm is thus applied to the selected word line W/L2, the non-selected cells connected to the selected word line W/L2 get stressed. However, because the non-selected cells are electrically isolated from the bit lines B/L1 and B/L2 and from the source line CSL, they can be floated by the voltage applied to the bit line select lines SSL1 and SSL2 and to the source line select line GSL. In this floated state, the channel voltages of the non-selected cells are self-boosted to be higher than the supply voltage by the pass voltage Vpass applied to the non-selected word lines W/Ln (1.ltoreq.n.ltoreq.16, n.noteq.2) and the program voltage Vpgm applied to the selected word line W/L2. Accordingly, a predetermined self-boosting voltage is retained at the channels of the non-selected cells, during the program operation, thereby preventing tunneling from the bulk, such that the non-selected cells are not programmed.
Since the program verifying operation consists of reading the respective cells to verify whether or not the selected cell is programmed, it is basically the same as the read operation which will be described below. It will therefore not be separately explained, but will be apparent from the following description of a read operation.
Referring to FIGS. 6 and 7C, a read operation for reading the state of cell data is performed by applying about 0.7V to the selected bit line B/L1 and by applying the supply voltage Vcc to the bit line select line SSL1, to the non-selected word lines W/Ln (1.ltoreq.n.ltoreq.16, n.noteq.2), and to the source line select line GSL. The ground voltage of 0V is applied to the non-selected bit line B/L2, the bit line select line SSL2, and the selected word line W/L2. Accordingly, if the threshold voltage of the selected cell is programmed to be over 0V, a current of the bit line will not flow through the cell. However, the bit line current will flow through the cell if the threshold voltage of the cell is erased and thereby lowered below 0V. The cell data value, corresponding to a logic level of "0" or "1", is then stored in a page buffer (not shown) and the stored data value can then be detected and amplified in a sense amplifier sequentially for each bit.
FIG. 8 shows a layout of one string block connected to a single bit line in the conventional NAND-type flash memory device employing the shared bit line technique and the self-boosting technique as shown in FIG. 6, in which like symbols are used for designating like or equivalent portions.
Referring to FIGS. 6 and 8, according to this conventional shared bit line NAND-type flash memory device, since two neighboring strings share one bit line, the integration level can be enhanced. Also, a sensing scheme using the self-boosting programming method and a page buffer can be employed. However, according to the high integration of the unit memory cells, the length of the active region where the source line is formed increases and the width thereof decreases, thereby increasing a resistance of the source line. Accordingly, the cell current is reduced by a bias of the source line during the read operation, which may result in a malfunction of the device.